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Instruction-level parallelism
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31	CCC Wkshp. on Advancing Computer Architecture Research (ACAR): What Now in ILP?, Seattle, WA, Sep[removed]In Search of Big Instructions Arrvindh Shriraman, Sandhya Dwarkadas, and Michael L. Scott Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-04-01 17:49:01 Central processing unit Classes of computers Parallel computing Microprocessors Microarchitecture Superscalar Reduced instruction set computing Instruction-level parallelism Very long instruction word Computer architecture Computing Computer hardware
32	Improving Memory Latency Aware Fetch Policies for SMT Processors Francisco J. Cazorla1 , Enrique Fernandez2 , Alex Ram´ırez1 , and Mateo Valero1 1 2 Add to Reading List Source URL: personals.ac.upc.edu Language: English - Date: 2005-05-12 12:36:37 Central processing unit Microprocessors Parallel computing Threads CPU cache Multithreading Instruction-level parallelism Branch predictor Multi-core processor Computing Computer architecture Computer hardware
33	RETROSPECTIVE: Software Pipelining: An Effective Scheduling Technique for VLIW Machines Monica S. Lam Computer Systems Laboratory Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2003-01-05 22:11:04 Computer engineering Software pipelining Very long instruction word Explicitly parallel instruction computing Instruction scheduling Instruction-level parallelism Central processing unit Multiflow Futures and promises Computing Computer architecture Compiler optimizations
34	A Coarse Grained Reconfigurable Architecture Framework supporting Macro-Dataflow Execution Add to Reading List Source URL: etd.ncsi.iisc.ernet.in Language: English - Date: 2014-04-23 02:19:41 Parallel computing Dataflow Instruction-level parallelism Multi-core processor Microarchitecture Compiler Central processing unit Granularity Computer architecture Computing Computer engineering
35	Compiler and Architectural Techniques for Improving the Effectiveness of VLIW Compilation J.P. Grossman Abstract Effective VLIW compilation requires optimizing across basic block boundaries. In this mildly opinionated pa Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2000-04-28 16:10:10 Parallel computing Computer engineering Compiler construction Very long instruction word Trace scheduling Software pipelining Branch predication Superscalar Instruction-level parallelism Computing Computer architecture Compiler optimizations
36	parently reordering instructions from nearby program regions, but even sophisticated compiler scheduling is fundamentally limited by the compiler’s inability to perfectly determine the programmer’s intent and its com Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:40 Parallel computing Microprocessors Threads Central processing unit Simultaneous multithreading Multi-core processor Multithreading Instruction-level parallelism Superscalar Computing Computer hardware Computer architecture
37	Appeared in the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October[removed]Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors Parthas Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:35:18 Computer engineering Cache CPU cache Computer memory Microarchitecture Out-of-order execution Instruction-level parallelism Pentium Pro Parallel computing Computer architecture Computer hardware Central processing unit
38	C:uments and SettingserDocuments Chips PDF Presentationsuesday_Conferencern.pdf Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:43:35 Tensilica Digital signal processing Classes of computers Very long instruction word Instruction-level parallelism SIMD Software pipelining Vectorization Computing Parallel computing Compiler optimizations
39	Journal of Instruction-Level Parallelism[removed]Submitted 2/02; published 6/03 Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-07-07 11:59:46 Formal sciences Branch predictor Randomness Instruction set architectures Alpha 21264 Entropy Hysteresis Counter DEC Alpha Computer architecture Electronic engineering Information
40	Journal of Instruction Level Parallelism[removed]Submitted 10/02; Accepted 04/03 Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-07-07 12:15:52 Assembly languages Compiler optimizations Instruction scheduling Instruction-level parallelism Very long instruction word Java bytecode Speculative execution Instruction set INT Computer architecture Computing Computer engineering

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